A conventional semiconductor device 100 shown in FIG. 9 includes an n-type nitride semiconductor substrate 110, a nitride semiconductor layer 120 stacked on the nitride semiconductor substrate 110, a drain electrode 132 covering a rear surface of the nitride semiconductor substrate 110, a source electrode 134 covering a front surface of the nitride semiconductor layer 120, and an insulation gate section 136 provided on a part of the front surface of the nitride semiconductor layer 120. The nitride semiconductor layer 120 includes an n-type drift region 121, p-type base regions 122, p-type channel regions 123, p-type contact regions 124, and n-type source regions 125. The drift region 121 is constituted of a horizontal drift region 121a and a vertical drift region 121b, and the vertical drift region 121b is at the front surface of the nitride semiconductor layer 120. Herein, the vertical drift region 121b may be referred to especially as a JFET region.
Each of the base regions 122 is disposed between the horizontal drift region 121a and a corresponding one of the channel regions 123, contains p-type impurities in high concentration, and is provided to suppress the corresponding channel region 123 from being punched through when the semiconductor device 100 is off. Each of the channel regions 123 is disposed at a position adjoining the vertical drift region 121b and situated at the front surface of the nitride semiconductor layer 120. Each of the contact regions 124 is disposed at the front surface of the nitride semiconductor layer 120 and electrically connected to the source electrode 134. Each of the source regions 125 is separated from the vertical drift region 121b by a corresponding one of the channel regions 123, disposed at the front surface of the nitride semiconductor layer 120, and electrically connected to the source electrode 134. A gate electrode 136b of the insulation gate section 136 is opposed to, via a gate insulation film 136a, a portion of each channel region 123 which separates the vertical drift region 121b and the corresponding source region 125. The gate electrode 136b of the insulation gate section 136 is electrically isolated and separated from the source electrode 134 by an interlayer insulation film 152.
When the semiconductor device 100 is on, an inversion layer is formed by a potential of the gate electrode 136b in the portion of each channel region 123 which separates the vertical drift region 121b and the corresponding source region 125, and electrons flow into the vertical drift region 121b from the source regions 125 through the inversion layers. The electrons that have flown into the vertical drift region 121b flow in the vertical drift region 121b in a vertical direction toward the drain electrode 132. Due to this, the drain electrode 132 and the source electrode 134 are electrically connected.
When the semiconductor device 100 is off, a depletion layer extends from each base region 122 and each channel region 123 into the vertical drift region 121b. The vertical drift region 121b is designed to turn into a pinch-off state where the depletion layers extending from its both sides connect to each other, during the semiconductor device 100 being off. Due to the vertical drift region 121b being pinched off electric field applied to the gate insulation film 136a of the insulation gate section 136 is alleviated, dielectric breakdown of the gate insulation film 136a is suppressed, and a breakdown voltage of the semiconductor device 100 is improved. It should be noted that when the semiconductor device 100 turns on, a potential of the vertical drift region 121b and a potential of the base regions 122 and the channel regions 123 become substantially equal, and the depletion layers disappear. A JFET structure is constituted of the n-type vertical drift region 121b and the p-type base regions 122, and another JFET structure is constituted of the n-type vertical drift region 121b and the p-type channel regions 123. Japanese Patent Application Publication No. 2015-041719 discloses an example of a semiconductor device including a vertical drift region (i.e., JFET region).